Method of manufacturing an intergrated circuit including steps for forming interconnections between patterns formed at different levels

ABSTRACT

A method of manufacturing integrated circuit is set forth in which a plurality of conducting patterns are formed on a substrate and dielectric material is deposited on the surface of the substrate and thereafter etched. The invention involves forming the dielectric material from two separate dielectric layers having respectively formed thicknesses such that upon etching the top dielectric layer is completely removed, while the underlying dielectric layer is removed according to the underlying type of conductive pattern.

The invention relates to a method of manufacturing an integrated circuitincluding the steps of:

a. forming on a substrate so-called first conducting patterns, whichcomprise first parts P₁ having at least a dimension W₁ of small valueand so-called second parts P₂ having larger dimensions and an uppersurface substantially coplanar with that of the first parts P₁ ;

b. depositing dielectric material having a thickness smaller on thefirst parts P₁ than on the second parts P₂ ; and

c. etching the dielectric material, which step is stopped from theappearance of the upper surface of the first parts P₁ in so-called firstinterconnection regions R₁.

The invention is used in the reduction of the surfaces of integratedcircuits showing several interconnection levels and in general in theformation of interconnections between patterns disposed at differentlevels.

The invention is used more particularly in the formation ofinterconnections between non-planer elements of micron or submicrondimensions.

U.S. Pat. No. 4,621,045 discloses a method of manufacturing anintegrated circuit, which includes the step of forming on a substrateconducting interconnection pads of large surface area and conductingpillars of small surface area. This method comprises the step of formingon the device thus formed a layer of a material having the propertiesboth of an electrical insulator and of a planarizing layer. Due to theseproperties of a planarizing layer, this layer has a thickness smaller onthe pillars of small surface area than on the pads of large surfacearea. This method moreover comprises the step of uniformly etching thedielectric planarizing layer, the etching step being stopped upon theappearance of the upper surface of the pillars.

Due to the fact that the dielectric deposited on the device comprisingthe large and the small patterns is formed by a single layer, it isnecessary that this layer has at least two properties at a time, i.e.that it is a good electrical insulator and is at the same timeplanarizing.

In fact, when the method is terminated, the upper conducting layer isfound to be only insulated from the lower conducting layer by aphotoresist layer, which is made insoluble by irradiation, or by a layerof polyimide, i.e. by a layer whose first and essential property is tobe planarizing, this layer consisting of a material chosen frommaterials which are also electrically isolating.

Now it has been found that for the manufacture of integrated circuits ofthe last generation these properties are not sufficient: the isolatingor insulating layer, which separates two conducting layers, mustmoreover have properties of passivating the semiconductor materialcovered by it, and properties of mechanical resistance, of temperatureresistance when subjected to later steps of forming the integratedcircuit and of resistance to ageing.

Nowadays the materials known for their planarizing properties have noneof these properties: they are not capable of ensuring the passivation ofthe semiconductor material if they are directly in contact with thelatter; they have a low mechanical resistance, a low temperatureresistance (at most 250° C.) and they age rapidly.

The manufacturer of integrated circuits will therefore refuse now toutilize any circuit including an ultimate layer of lacquer or resin.Therefore, the method known from the aforementioned patent documentbecomes inappropriate due to the fact that it results in a circuit whichis no longer in manufacturing synergy with the new integrated circuits.

Therefore, it should be avoided to maintain such a layer among theultimate layers.

Subsequently, a problem arises in the case in which these circuits arefurther non-planer. Thus, this state of the art does not indicate theformation of a connection between a pattern of small (micron orsubmicron) dimensions and another pattern of arbitrary dimensionsformed, however, on a lower layer of the circuit, which happens whenconnections should be formed between, for example, electrodes ofdifferent non-planer transistors.

An object of the invention is to provide a method of manufacturingresulting in an integrated circuit without unreliable ultimate layers,such as the isolating layer known from the aforementioned patent, and onthe contrary is provided with isolating layers having better electricaland mechanical performances.

Another object of the invention is to provide a method of manufacturingresulting in a circuit, in which the isolating layer, or layers, is, orare, also a passivation layer, or layers.

Another object of the invention is to provide a method which can be usedin the manufacture of both planar and non-planar circuits.

Another object of the invention is to provide a method which results inthe planarization of the device even if the latter originally wasnon-planar.

Another object of the invention is to provide a method which permitsforming openings without the necessity of using opening masks on all thechosen patterns of a circuit, and in the chosen interconnection regions,irrespective of the original dimension of the pattern on which anopening should be formed and irrespective of the original degree offlatness of the substrate on which it is formed.

Another object of the invention is to provide a method which permitsforming openings and hence interconnections directly with patterns ofmicron or submicron dimensions.

Another object of the invention is to provide a method of manufacturingan integrated circuit in manufacturing energy with the integratedcircuits of the last generation.

Another object of the invention is to provide a method which is simpleand inexpensive in view of all the advantages offered by it.

According to the invention, these objects are achieved by means of amethod of manufacturing an integrated circuit of the kind described inthe opening paragraph and characterized in that for this purpose thedeposition of the dielectric material comprises the 15 deposition of afirst dielectric layer D₁ covering the device with a uniform thicknessH_(d) and substantially equal to or larger than the height H_(m) of thefirst parts P₁ followed by the deposition of a second dielectric layerD₂ having a thickness smaller on the first parts P₁ than on the secondparts P₂, and in that the etching of the dielectric material comprises afirst step which is stopped upon appearance of the upper surface of thefirst dielectric layer D₁ above the first parts P₁ and a second stepduring which the first dielectric layer D₁ is etched at a rate higherthan or equal to the rate of etching of the second dielectric layer D₂.

An advantage resulting immediately from this method is that, due to thefact that the first dielectric layer D₁ is deposited in a uniformthickness, among uniformly deposited materials compounds can be foundwhich are capable of forming appropriate passivation layers.

Another advantage is that among the materials likely to be deposited ina uniform layer D₁ materials can be found which have beside the propertyof passivation better performance of mechanical strength and betterperformances as an electrical isolator than the isolating layer knownfrom the state of the art, and in general, then the layers deposited influid form or as planarization layers.

Another advantage due to the fact that the first dielectric layer D₁ isdeposited in a uniform thickness is that among the materials capable ofbeing deposited in a uniform thickness materials can be found which notonly have the advantages mentioned above, but also are in manufacturingsynergy with all the modern integrated circuit technologies and withthose which already have been selected to be used in the near future.

Another advantage is that without the use of a mask openings can beprovided directly in patterns of micron or sub-micron dimensions.

Another advantage is that a planarization layer D₂ of lacquer or resincan be eliminated.

In one embodiment, this method is characterized in that the formation ofthe first conducting patterns

comprises the formation of second parts P₂ provided in so-called secondinterconnection regions R₂ with parts of reduced width or appendices P'₁that can assimilate with the first parts P₁ having at least onedimension substantially equal to W₁ and an upper surface substantiallycoplanar with that of the first parts P₁.

An advantage is that openings can be formed in the second parts P₂ oflarge dimensions without supplementary steps, that is to say during thesame step as the step of forming in the parts P₁ openings having atleast one small dimension substantially equal to W₁ and an upper surfacesubstantially coplanar with that of the first parts P₁.

An advantage is that openings can be provided in the second parts P₂having large dimensions without supplementary steps, that is to sayduring the same step as the step of providing openings in the parts P₁which have at least one small dimension and moreover without the use ofanother mask than that necessary for forming the second parts P₂ in thefirst step of the method.

Another advantage is that the openings both in the first parts P₁ and inthe parts P'₁ of the parts P₂ occupy a very limited surface of thecircuit.

Another advantage is that as interconnection regions R₂ for the secondparts P₂ regions can be chosen which can be remote from the parts P₂ orcan be situated in the zones which, without the use of the method, wouldhave been lost, which possibilities offers new possibilities ofarranging the design of the circuits, which are profitable for thedesigner of integrated circuits.

In another embodiment, the method is characterized in that the formationof the first conducting patterns comprises the formation of so-calledthird parts P₃ having arbitrary dimensions and an upper surface at alevel below that of the upper surface of the first parts P₁ and theformation of conducting lines L₁ having so-called contact zones with thethird parts P₃ on the one hand and in the so-called thirdinterconnection regions R₃ on the other hand parts of reduced width orappendices P"₁ which assimilate with the first parts P₁ having at leastone dimension substantially equal to W₁ and an upper surfacesubstantially coplanar with that of the first parts P₁.

An advantage is that the method can be used both in planar circuits andin non-planar circuits.

Another advantage is that, in order to raise the level of parts P₃, itis much easier to form, lines rather than pillars, indicated by thestate of the art. In fact, in the formation of the conducting lines L₁ ,the method of masking is not critical.

Another advantage is that the interconnection region R₃ can be chosen infavourable zones of the circuit, as has been stated for the choice ofthe interconnection regions R₂.

Another advantage is that all the interconnection regions of the circuitcan be brought to the same level, irrespective of the original level ofthe parts P₃, and that the openings can be formed in a single step andwithout a mask, provided that the parts P₁, P'₁, P"₁ have at least oneor only one dimension of smaller value than the other dimensions of thefirst patterns at this level.

In a further embodiment, the method is characterized in that thethickness H_(d) of the first dielectric layer D₁ is chosen as a functionof the height H_(m) of the first parts P₁ and the difference H_(l)between the first and second thicknesses of the second dielectric layerD₂ so as to satisfy the condition:

    H.sub.d =H.sub.m.sup.2 (H.sub.m -H.sub.l).sup.-1,

and in that the ratio S between the rate of etching the first dielectriclayer D₁ and the rate of etching the second dielectric layer D₂ in thesecond etching step is chosen so as to satisfy the condition:

    S=(H.sub.d -H.sub.m)H.sub.l.sup.-1 >1,

An advantage is that at the end of the process, the device can beplanar, while the material forming the remaining dielectric layer D₁does not form part of the so-called planarization materials.

Another advantage is that, in the case of originally non-planarcircuits, the method offers the possibility of obtaining at the end ofthe last step a device which is nevertheless planar.

In a further embodiment, the method is characterized in that the firstparts P₁ are patterns of micron or submicron dimensions, for examplegates of field effect transistors or emitters of bipolar transistors,and in that the second parts P₂ are electrodes of active components orinterconnection lines, and in that the third parts P₃ are electrodes ofnon-planar active components, for example bases or collectors of bipolartransistors.

The invention therefore permits the miniaturization of both non-planarand planar circuits, simplification of their manufacture, improvement oftheir properties and reduction of their manufacturing cost.

In order that the invention may be readily carried out, it will now bedescribed more fully with reference to the accompanying drawings, inwhich:

FIGS. 1a, 1b, 1c and 1d show the first steps of the method according tothe invention, in the case in which the first patterns comprise coplanarparts P₁ and P₂ ;

FIGS. 2a and 2b show the following steps of the method in a firstvariation where the first patterns comprise coplanar parts P₁ and P₂ ;

FIGS. 3a and 3b show the following steps of the method in a secondvariation and in the case in which the first pattern comprise coplanarparts P₁ and P₂ ;

FIGS. 4a and 4b show the heights of the layers used in the steps leadingto the second variation of the invention;

FIG. 4c is a plan view of FIG. 4b and illustrates that the whole surfaceof the parts P₁ can be exposed at this stage of the method;

FIG. 5a is a plan view of an interconnection between a first part P₁disposed at a first level of the circuit and a third part P₃ disposed ata second level of the circuit lower than the first level obtained bymeans of the method according to the invention;

FIGS. 5b and 5c show in sectional view such an interconnection, whereFIG. 5c is a sectional view taken on the axis I--I of FIG. 5a; and

FIGS. 6a and 6b show in plan view examples of interconnections betweenvarious parts of integrated circuits obtained by means of the methodaccording to the invention.

The method according to the invention is used more particularly forformation of interconnections between metallic patterns (P₁, P'₁, P"₁)disposed at a first level N₁ of a circuit by means of theinterconnection lines of second patterns L₂ formed in a metallic layerseparated from the first patterns of the first level N₁ by a dielectriclayer D₁.

The present invention proposes a method which permits forming openingsor VIAs in the dielectric layers D₁ on the parts P₁, P'₁, P"₁ of thepatterns, which have at least one of their dimensions W₁ parallel to thefirst level N₁ and with a small value with respect to the values W₂ ofthe other parts P₂ of these patterns. These other parts remains coveredby the dielectric layer D₁, without the use of conventional masks. Suchmasks are obtained and positioned only with great difficulty and aretherefore expensive when carrying out the method.

In one embodiment, the method according to the invention first comprisesthe following successive step.

First is the step of (A) forming, as shown in sectional view in FIG. 1a,at the level N₁ of the integrated circuit, metallic or semiconductorpatterns having parts P₁ and P₂.

The first level N₁ can be the upper surface of a substrate S of asemiconductor material, such as silicon or gallium arsenide.

The first level may also be a second interconnection level which isalready formed. On the other hand, the first parts P₁ may consist of asemiconductor material, such as an emitter of a bipolar transistor.

The parts P₁ have a height H_(m). Here only the case is considered inwhich the parts P₁ have a height H_(m) larger than or substantiallyequal to the height of the parts P₂.

The parts P₁ are moreover defined by a lateral dimension W₁ and theparts P₂ are defined by a lateral dimension W₂. The object of theinvention is to provide openings or VIAs in the parts P₁ in the case inwhich they have at least one dimension W₁ smaller than or approximatelyequal to half the dimension W₂ of the parts P₂. In the embodiment shownin FIG. 1a, the first part P₁ are is separated from the second part P₂by a distance L. However, this is a particular case. The parts P₁ and P₂can be joined together, as shown in FIGS. 6a and 6b.

The materials used to form the conducting patterns having parts P₁ andP₂ may be any metal usually employed in the manufacture of integratedcircuits, such as: AuGe, NiCr, TiPtAu or W_(n). If the gate of a (fieldeffect or bipolar) transistor is concerned; these materials may also bealuminium or polysilicon. If interconnection lines are concerned; thesematerials may also be any semiconductor.

The heights H_(m) can lie in the range of from a few hundred nms toseveral microns.

If at this first level N₁, elements, such as interconnection lines 21 or31, as shown in FIG. 6a, are situated, which by their dimensions are notin the category of the first parts P₁, because such parts already exist,smaller than those shown on which VIAs are provided, it is thensufficient to provide on these lines or in part of these elements a partof reduced width, such as an appendix P'₁, 21' and 31', respectively,having suitable dimensions W₁ so that the region of the part of reducedwidth or of the appendix P'₁ is caused to enter the category of thefirst patterns P₁. In the later steps of the method, the region of thepart of reduced width or of the appendix will automatically be theregion of location of the desired VIA.

Thus, a part of reduced width of an appendix P'₁ can be readily formedon interconnection lines (see FIG. 6a), but also an appendix P'₁ can bereadily provided at the end of an electrode 121 or 122 of, for example,a transistor. Thus, FIG. 6b shows the appendices P'₁ and 121' and 122',respectively, at the ends of the source and drain electrodes S and D,respectively, of a field effect transistor, whose gate G constitutes apart P₁.

Therefore, according to the invention, instead of providing widenedparts to obtain VIAs, most frequently parts of reduced width will beprovided in regions designated by R₁ or interconnection regions for theparts P₂. This results in a quite new way of working for the designer ofintegrated circuits.

It should be noted that the opening will be provided in the whole regionin the category P₁, for example the whole upper surface of the gate G ofa field effect transistor (see FIG. 6b) or the whole upper surface ofthe line part of reduced width 21', 31', 121', 131' (see FIGS. 6a, 6band FIG. 4c). Thus, the whole part P₁ is a possible interconnectionregion designated by R₁ as shown in FIG. 5A.

This results in one of the advantages of the invention, which consistsof a substantial saving in surface area, especially for the first layersof the integrated circuit. These layers are generally also the densestlayers and determine the final dimension of the substrate to be used andnew facilities for the designer of integrated circuits in providing thelocation of the second patterns L₂.

Next is the step (B) Deposition, as illustrated in FIG. 1b, of a uniformlayer of a first kind of dielectric D₁. In order to obtain this uniformlayer, the dielectric D₁ must be chosen among the materials which aredeposited by a growing method, for example by a chemical action in thevapour phase known under the designation of CVD or PECVD, or by cathodesputtering. The term "uniform layers" is to be understood to mean thatthe thickness H_(d) of the dielectric D₁ is the same on the first partsP₁, on the second parts P₂ and between the parts P₁ and P₂. On the otherhand, the thickness of this dielectric layer D₁ will be chosen to be:

H_(d) ≧H_(m)

H_(m) being the height of the first parts P₁ with respect to the levelN₁, which essentially has for its object to cover entirely all thepatterns of this first level N₁.

However, the thickness of the dielectric D₁ in this step depends uponthe object that should be attained subsequently.

In fact, according to the invention, the method can be carried out intwo variations. The first of these variations permits obtaining a localplanarization around the first parts P₁ with the second parts P₂nevertheless remaining covered by the dielectric layer D₁ forming a MESAon these parts P₂, as shown in FIG. 2a. The second of these variationspermits obtaining a general planarization of the device, the secondparts P₂ being covered by the dielectric D₁ and windows being openedabove the first parts P₁. These windows have the form of a basin ofsmall depth, whose bottom is constituted by the surface of these firstparts P₁, as shown in FIG. 3a. If the second variation is chosen, duringthis step of forming the dielectric layer D₁ a thickness

    H.sub.d =H.sub.m.sup.2 (H.sub.m -H.sub.l).sup.-1

of this material must be deposited.

In this relation, H_(l) is the difference in thickness which will beobtained during the following step (C) between the first thickness of asecond layer of dielectric D₂ above the first parts P₁ and the secondthickness of the second layer D₂ above the second parts P₂ to carry outthe second variation of the invention.

The value of H_(l) can be found either by experiments or by modellingand is of the form:

    H.sub.l =k.H.sub.m.sup.2 (W.sub.2 -W.sub.1)(W.sub.1 +H.sub.m).sup.-1 (W.sub.2 +H.sub.m).sup.-1.

Materials particularly suitable to obtain the layer D₁ can be chosenamong silica (SiO₂) or silicon nitride (Si₃ N₄), which are isolatorsvery frequently used in integrated circuit technology. As the layer D₁is an ultimate layer, it is absolutely necessary that this dielectrichas a recognized quality.

The next step is (C) Formation of a second dielectric layer D₂, as shownin FIG. 1c. This dielectric layer D₂ must be chosen among the materialsextending in the fluid form, which permits obtaining a first thicknesson the first parts P₁ and a second thickness on the second parts P₂. Thesecond thickness on the second parts will be especially larger than thefirst thickness on the first parts P₁. The difference between thesethicknesses will be H_(l), whose formula has been given above. Therewill be a so-called third thickness also larger than the first thicknessbetween the patterns if they are mutually separated. In the equation forH_(l), k is a constant which depends upon the material chosen to obtainthis second dielectric layer D₂. In order to obtain the seconddielectric layer D₂ extending in fluid form, polymerisable resins, suchas an epoxy resin or further a photosensitive lacquer, can be chosen ofwhich here the properties known for the photolithography will not beutilized, but only the fact that the photosensitive lacquers aredeposited in a smaller thickness on small patterns than on largepatterns, when they are deposited in certain conditions, is utilized.

When considering the distribution of the thicknesses of such a layer D₂as a function of the dimensions W of the different patterns, it is foundthat the thicknesses increase according as to increase in the dimensionsW of the patterns, when the layer D₂ is deposited under the conditionsdefined below. Therefore, in order to achieve the object of theinvention and to clearly distinguish the thicknesses of dielectric D₂formed on the different parts of the patterns, it is necessary thatthese parts have greatly different dimensions. These differences indimensions will be sufficient when W₂ is larger than or approximatelyequal to twice W₁.

This distinction can be readily made in integrated circuits due to thefact that in the original design there are elements or parts of patternshaving greatly different dimensions or due to the fact that a part ofreduced width or an appendix P'₁ can always be provided at the locationat which a VIA should be opened.

For example, in order to obtain the dielectric layer D₂, a positivephotosensitive lacquer AZ 4110 (Shipley Society) may be chosen, which isdeposited under the following conditions:

speed of rotation 4500 revolutions/min for a duration of 40 seconds;

drying of the lacquer at a temperature of 90° C. for 30 minutes

exposure to ultraviolet radiation having a wavelength of 300 nm with anenergy of 900 mJ/cm² ; and

successive annealings at 90° C., 120° C., 180° C. and

In the case in which this photosensitive lacquer is used on a layer ofsilica (SiO₂), the coefficient k in the equation for H_(l) is of theorder of 1/2.

The total planarization of the device by means of this layer D₂ is notrequired, which could also be obtained in other deposition conditions.

A further step is (D) Carrying out a first step of dry etching, forexample of by reactive ion etching, to etch the second dielectric layerD₂ at a uniform rate. This first step of dry etching will be stopped assoon as zones of the first dielectric layer D₁ will appear at thesurface of the device. Methods are known to those skilled in the art forobtaining automatic stopping of the etching treatment.

If the positive photosensitive lacquer mentioned above has been used, auniform etching of this lacquer will be obtained by means of O₂ gasmixed with the vectorial gas N₂ at an etching rate of the order of 145nm/min. A uniformity of the order of ±1% is aimed at.

Beyond this step, the etching conditions will be different dependingupon whether one or the other of the variations of the invention are tobe used. At the end of step (D), the device as shown in FIG. 1d insectional view or in FIG. 4a in sectional view has a layer of dielectricD₁ still unattacked, covered by a thickness H_(l) of the layer ofdielectric D₂ above the parts P₂. Above the first parts P₁, thisthickness is zero, the layer of dielectric D₁ then being level with thesurface.

From this device a second step of dry etching or reactive ion etchingcan be started, which second step can be carried out in two differentways, leading to the two variations of the device according to theinvention.

The first variation is obtained after step E₁ and the second variationis obtained after step E₂ both described below. The choice between thefirst and the second variation is made as a function of the residualthicknesses H_(R) of dielectric D₁ that the designer of integratedcircuits wants to maintain at the surface of the second parts P₂ havinglarge dimensions.

In fact, for example, the parasitic capacitances that can be introducedinto the circuit between the parts P₂ on the first level N₁ and themetallic patterns situated at a higher level, i.e. at the surface of thedielectric D₁ at the end of the method according to the invention (seeFIG. 2b and 3b) depend upon the thickness H_(R) of the residualdielectric D₁ maintained at the surface of the parts P₂.

In the following steps of the method according to the invention leadingto the first variation, there is thus the step of:

(E₁) carrying out a so-called second step of dry etching, for examplereactive ion etching, at a rate of etching the second layer-D₂ equal tothe rate of etching the first layer D₁. This etching is stopped upon theappearance of the upper surface of the first parts P₁. A layer of thefirst dielectric D₁ remains at the surface of the second parts P₂forming a MESA, both in the case in which the first parts P₁ have thesame height H_(m) as the second parts P₂ and in the case in which theheight H_(m) of the first parts P₁ is larger than that of the secondparts P₂. The openings formed at the surface of the first parts P₁ arethen particularly suitable to constitute VIAs. The layer D₂ has beencompletely eliminated. As already stated above, those skilled in the artwill employ, one of the methods known from the prior art for attainingthe automatic stopping of the etching treatment.

The etching selectivity S defined as the ratio between the rate ofetching layer D₁ and the rate of etching layer D₂ must therefore beequal to 1.

In order to obtain this selectivity S=1, in the case given by way ofexample in which the layer of the second dielectric D₂ is made of thephotosensitive lacquer mentioned above, and in which the layer of thefirst dielectric D₁ is made of silica (SiO₂), the method according tothe invention can be carried out by means of gases:

SF₆ with a flow rate of 2.14 SCCM,

CHF₃ with a flow rate of 14.3 SCCM,

N₂ with a flow rate of 19.3 SCCM.

The etching rates obtained by this system are of the order of 30.5nm/min for the first dielectric D₁ and of 31 nm/min for the seconddielectric D₂.

For first parts P₁, whose height is:

H_(m) ≃0.5 μm

and the smallest lateral dimension, i.e. measured parallel to the planeof the first level N₁, is:

W₁ ≃0.8 μm,

and for parts P₂ of the same height and having lateral dimensionsmeasured in the same plane:

W₂ ≃5 μm,

these patterns being, as the case may be, mutually separated by adistance:

L≃5 μm;

the residual thickness of the dielectric D₁ is equal to the differenceH_(l) of the dielectric D₂, which originally between the parts P₂ andP₁, i.e.

H_(R) ≃H_(l) ≃0.25 μm.

The second variation of the device according to the invention isobtained after the following step:

(E₂) carrying out a so-called second step of dry etching, for examplereactive ion etching, at a rate of etching the first dielectric D₁higher than the rate of etching the second dielectric D₂. Under thiscondition, the first dielectric D₁ is attacked in the openings in thesecond dielectric D₂ above the first parts P₁. Due to the fact that thefirst dielectric D₁ is etched at a rate higher than that of the seconddielectric D₂, basins are obtained above the parts P₁ and have edges ofa cavity turned toward the exterior of the device and having a smalldepth. The etching is stopped as soon as the upper surface of the firstparts P₁ appears in these basins, while carrying out a known method ofstopping the etching treatment.

The advantage of this variation is that, by correctly choosing theselectivity S of etching the electric layers D₁ and D₂, a fully planardevice can be obtained, which only has openings in the form of basins atsurface of the parts P₁, these openings being particularly suitable toform VIAs.

If the dimensions and materials of the embodiment described above aremaintained, i.e.:

H_(m) ≃0.5 μm,

W₁ ≃0.8 μm,

W₂ ≃5 μm,

L≃5 μm, as the case may be,

H_(l) ≃0.25 μm,

in order to obtain the planarization of the device under the conditionsshown in FIGS. 3a and 3b, the thickness of the deposited dielectric D₁must be:

H_(d) ≃H_(m) ² (H_(m) -H_(l))⁻¹

and the selectivity:

S≃(H_(d) -H_(m)) H_(l) ⁻¹.

When choosing

H_(d) ≃1 μm,

this results, in order to obtain a planar device, in etching conditionsleading to

S=2.

For dielectric layers D₁ and D₂ constituted respectively by silica(SiO₂) and positive photosensitive lacquer, mentioned above, theseetching conditions are obtained with reactive ion etching by means ofthe gases:

SF₆ with a flow rate of 1.9 SCCM

CHF₃ with a flow rate of 24.5 SCCM

N₂ with a flow rate of 9.3 SCCM

at a high pressure and power.

The etching rates are then of the order of 23.5 nm/min in the seconddielectric D₂ (positive photosensitive lacquer) and of 45.0 nm/min inthe first dielectric D₁ (SiO₂).

The residual thickness H_(R) of the first dielectric D₁ on the secondparts P₂ is in this case of the order of 0.45 μm (see FIG. 5b).

The preceding steps E₁ and E₂ of the manufacturing method according tothe invention may also be carried out if the first dielectric D₁ isdifferent, for example silicon nitride (Si₃ N₄). In the case of step E₂,a selectivity S will be chosen which is higher than for silica (SiO₂),for example S=3 or 4.

As is apparent from FIGS. 4a and 4b showing the thicknesses used duringthe steps D and E₂ in the case in which S=2, at the end of the step E₂the thickness of the residual thickness of the dielectric D₂ above thesecond parts P₂ depends only upon the initial thickness H_(m) of thefirst parts P₁ and upon the thickness H_(d) of the dielectric D₁ ;

H_(R) ≧H_(d) -H_(m).

On the other hand, no second dielectric D₂ is left at the end of theprocess.

It should further be noted that for the gases used for the second dryetching step the first dielectric layer D₁ must be etched selectively soas to readily permit stopping the process as soon as the upper surfaceof the first parts P₁ appears.

In order to obtain the interconnection between the first parts P₁ on thefirst level N₁ and the patterns L₂ situated at a higher level of thecircuit, a step can then be carried out of:

(F) forming a mask on the second interconnection level and depositing ametallic layer 15 in the openings of this mask (see FIGS. 2b and 3b).This deposition can take place, for example, by evaporation, by cathodesputtering, or by electrolytic growth by means of metals chosen amongthe metals apt to form the first patterns of the first level and withthicknesses that can vary from a few tens of nms to a few microns. Thepatterns L₂ of this metallic layer 15 of a higher level are arranged soas to present regions situated at the surface of the opened VIAs duringsteps E₁ / and E₂ /, thus establishing the electrical contact betweenmetals at N₁ and the higher level otherwise isolated by the residualthickness of the dielectric layer D₁ or connecting by conductive linesL₂ parts P₁ and P'₁ to each other.

FIGS. 6a and 6b show in plan view different devices obtained by the useof the method according to the invention.

FIG. 6a shows interconnection between lines. The parts P₂ are shown hereby the lines 21 and 31 formed at a first level N₁ and by the line 41also situated at this first level. FIG. 6a is a simplifiedrepresentation of the device, but it is shown on the scale of a possibleexample of application of the method according to the invention. Thedistance corresponding to 1 μm is represented in this FIG. 6a. In thisexample, the lines 21 and 31 should be interconnected by a line 25formed at a higher level. In order to apply the method according to theinvention, because lines 21, 31 and 41 have transverse dimensions whichare approximately equivalent and indicated as W₂, during formation ofthe lines 21 and 31 appendices P'₁, 21' and 31' are provided at the endof these lines with a dimension W₁ to be assimilated to parts P₁. Whencarrying out the method according to the invention, VIAs areautomatically opened in these parts of reduced width 21' and 31' and theline 25 (L₂) can then be formed in the metallic layer 15 at a higherlevel with a signal mask due to the fact that a mask for opening VIAs isnot necessary.

FIG. 6b shows diagrammatically in plan view and not to scale aninterconnection line 125 (L₂) at a higher level formed above a VIAopened by the method according to the invention in the gate G formed bya part of the P₁ type, for example of submicron dimensions of the orderof W₁ =0.25 μm for a field effect transistor, in which S and D are thesource and the drain, respectively. The electrodes S, G and D are formedat the first level N₁ and S and D have dimensions W₂ considerably largerthan G, for example 5 to 8 μm, and are formed by the second parts P₂.The electrodes S and D are moreover spaced from G by a distance L of theorder of 1 to 2 μm, i.e. of the order of twice the transverse dimensionW₁ of the gate G. According to the invention, the interconnection lineL₂ 125 can be connected directly to the gate G above the gate fingerwithout it being necessary to provide at one end of the finger a pad oflarge surface area for opening the VIA, as is known from the state ofthe art. This interconnection line 125 may also be arranged at any areaof the gate G because the whole surface of the latter is exposed by thismethod. This results in a design facility for the designer of integratedcircuits. According to the invention the interconnection is formedbetween G and the line 125 with a substantial saving in space. Thus,several gate fingers can be connected in the case of interdigitatedtransistors.

It is clear that the method according to the invention can be used alsoto interconnect, for example, the emitters of bipolar transistors (notshown). In fact, the upper surface of these electrodes is slightlyhigher than the upper surface of the base and the collector of the sametransistor. Consequently, the height H_(m) of the emitter considered asthe first part P₁ is larger than that of the base and of the collectorconsidered as third parts P₃. Moreover, the dimensions of the emitter ofthe order of 1 to 2 μm are very suitable for use in the invention, inview of the dimensions of the base and of the collector, which are theorder of 3 to 4 μm. Here the use of the invention is of particularimportance to obtain a residual thickness H_(R) of dielectric above thebase and the collector sufficient for their isolation. Openings in theseelectrodes can then be formed by a method which will be describedhereinafter.

With regard to a planar transistor of the kind shown in FIG. 6b, inwhich the three electrodes S, G and D have approximately the same heightH_(m), but not all have dimensions for the first parts P₁, it issufficient to provide at the level of the other electrodes S and D 122and 121, respectively, an appendix 122' and 121' of small dimension W₁,to which a VIA will be opened automatically by the use of the methodaccording to the invention, such as for example, by the use of thesecond variation (step E₂, see FIG. 6b). All the connections can then beformed during the same steps (E₂ +F), for example by means of the line124 (L₂) on the part 122' and by means of the line 123 (L₂) on the part121'. The lines 124 and 123 are constituted, for example, by the layer15.

The applications of the invention in the field of integrated circuitsare therefore numerous because a part of reduced width P'₁ can be,provided with a metallic part at the first level N₁, on which a VIAshould be opened, even where this part has not the dimensions desired toenter the category of the conditions imposed on the dimensions of thefirst parts P₁.

The method according to the invention may also be used in the formationof interconnections between parts of patterns arranged at the firstlevel N₁ and other parts arranged at a lower second level N₂, in theformation of integrated circuits, especially micron or submicroncircuits, which are non-planar.

The different patterns are metallic or semiconducting. In this example,they are metallic.

As shown in FIG. 5a in plan view and in FIGS. 5b and 5c in sectionalview, as well as in FIG. 1a in sectional view, the first parts P₁ arepresent at the first level N₁, which have at least one small dimensionW₁ measured parallel to the level N₁, and the second parts P₂ of largerdimension W₂ are also present at this level. At the a second lower levelN₂ so-called third parts P₃ of arbitrary dimensions are present.

The object of this method is to form interconnections between the partsP₃ and P₁ of a nonplanar circuit, to protect the circuit by a dielectriclayer of high quality D₁, to form openings at the surface of the firstparts P₁, and to form interconnection lines L₂ with the other patternsat the surface of the dielectric layer D₁ to connect to other parts P₁or to parts equivalent to P₁. This dielectric layer D₁ is preferablyboth planar and unexposed at the patterns P₂ during the operation ofproviding openings in the patterns P₁. This operation is carried outwithout using a conventional mask, which is provided and positioned onlywith difficulty so that the cost required for this is high.

For this a embodiment, the method according to the invention firstcomprises step (A) already described above. However, in this step,simultaneously with the step of defining the design of the parts P₁ andP₂, locations or interconnection regions R₃ for the patterns P₃ aredefined (see also FIGS. 5) and parts P₁ of metallic or semiconductingpatterns are formed at the second level N₂ of the integrated circuit, asshown in sectional view in FIGS. 5b and 5c, or in plan view in FIG. 5a.FIG. 5c is a sectional view taken on the axis I--I of FIG. 5a.

These parts P₃ are not only formed at a lower level N₂ of the circuit,but also their upper surface is arranged in a plane lower than the uppersurface of the parts P₁ so that a planar interconnection between theparts P₁ and P₃ is not possible.

The first level N₁ can be the upper surface of a stack 11 ofsemiconductor layers of different materials or of different conductivitytypes formed on a substrate 10 of a semiconductor material, such assilicon or gallium arsenide or another material of the group III-V. Inthe whole following description, these support layers will be designatedby S for the sake of simplicity of writing.

The level N₂ can be constituted by one of the different layers of thestack 11, which forms the level N₁. The parts P₃ can be formed by anymeans known to those skilled in the art. For example, the substrate 10or the stack 11 may be etched down to the level N₂ in the opening of amask or by self-alignment on other patterns. Subsequently, the parts P₃are formed at the level N₂ by means of one of the materials previouslymentioned for formation of the parts P₁ and P₂.

The dimensions of the parts P₃ may be arbitrary. The parts P₃ may be,for example, collector or base electrodes of bipolar hetero-junctiontransistors (HBT), and the parts P.sub. then are either emitterelectrodes of such transistors or connection lines of the first levelN₁. The parts P₃ may also be gates of buried gate field effecttransistors.

A problem then arises for using the invention as described above due tothe difference in height between the upper surfaces of the parts P₃ andof the parts P₁, which difference is generally due to the differencebetween the levels N₁ and N₂.

Therefore, there is preferably interposed between the step A describedabove and step B above the additional step of:

(A') forming, as the case may be, a step ST between the third part P₃and its respective interconnection region R₃ of the first level orsubstantially of the first level N₁ (cf. FIG. 5b).

The upper surface of the step ST is at an intermediate level between thelevel N₁ and the level N₂. More than one step can be provided if thedifference in height between the level N₁ and the level N₂ is great.

If the part P₃ to be interconnected is the collector of a transistorHBT, the upper level of the step ST can be that of the base of thetransistor and the step can be provided by etching jointly with theformation of this base (see FIG. 5b).

If the part P₃ to be interconnected is the base of a transistor HBT, theproblem of the formation of the step ST can be avoided (see FIG. 5c).

Irrespective of whether the (one or several steps) ST prove to benecessary or not necessary, it may otherwise be necessary formaintaining an interconnection region R₃ at the level N₁ orsubstantially at the level N₁ for the pattern P₃ to form a pad 12, withan upper surface substantially at the level N₁ (see FIGS. 5b and 5c).This pad 12 is formed by an arbitrary etching method adapted to thematerial of 10 or 11.

Otherwise, if the difference between the level N₁ and the level N₂ issmall, a simple inclination obtained by etching can be sufficient topermit the following step, which is interposed between the step A' andthe step B, i.e.

(A") Forming a first conducting line L₁ connecting the third part P₃ toits interconnection region R₃. The steps ST are provided when thedifference in level between N₁ and N₂ is great and would involve therisk of creating faults in the line L₁. Therefore, the person skilled inthe art would provide such a number of steps as is necessary. However,it is preferable, in order not to lengthen the process to carry out theformation of the steps, jointly with the formation of other levelsindispensable for forming the non-planar circuit.

During its manufacture, the first conducting line L₁ is formed with adesign according to which it comprises in the interconnection region R₃, for example, a part having a reduced width or an appendix P"₁ (13)(see FIGS. 5) having at least a transverse dimension W₁ suitable topermit its classification in the category of the first patterns P₁.

This conducting line L₁ may be made of any material conventionallyemployed in integrated circuit technology for forming interconnectionlines. This material may be deposited in the opening of a mask by aconventional method known to those skilled in the art.

At this stage of the method, reference is made to the step B describedabove. However, each time reference is made to a part P₁, also the partsP'₁ and P"₁, which have the same properties, are included.

On the other hand, when carrying out the method, in general and moreparticularly in the case of non-planar circuits the variation ispreferred which results in the planarization of the first dielectriclayer D₁ and hence of the device as a whole.

Thus, according to the method, due to the upper metallic layer 15,interconnections L₂ can be formed between the parts P₁ or P'₁ or P"₁ ininterconnection regions chosen as favourable regions, R₁, R₂ and R₃,respectively. Further, since the surface of the remaining dielectriclayer D₁ may be planar, at its surface, besides the layer 15, any kindof patterns other than interconnection lines may be formed in such amanner that the method according to the invention can be repeatedseveral times.

I claim:
 1. A method of manufacturing integrated circuits havingimproved electrical and mechanical properties comprising the steps of(a)forming first conducting patterns on a substrate, said first conductingpatterns including at least one first conducting portion having adimension W₁ and at least one second conducting portion having adimension W₂ substantially larger than W₁, said first conducting portionand second conducting portion having substantially coplanar uppersurfaces; (b) at least some of said second conducting portions beingformed with appendices of reduced width, said appendices having adimension substantially equal to W₁, and said appendices having an uppersurface substantially coplanar with the upper surfaces of said firstconducting portions; (c) depositing a first dielectric layer over saidconducting patterns and said substrate, said first dielectric layerbeing a passivating material, and said first dielectric layer having auniform thickness, said uniform thickness being at least equal to athickness of said at least one first conducting portion; (d) thereafterdepositing a second dielectric layer over said first dielectric layer,said second dielectric layer also being passivating and having a smallerthickness over said at least one first conducting portion than over saidat least one second conducting portion; (e) etching said seconddielectric layer until said first dielectric layer over said at leastone first conducting portion appears; (f) thereafter etching said firstdielectric layer at an etch rate greater than the etch rate of saidsecond dielectric layer to form openings to said first conductingportions while said second conducting portions remain covered by athickness of said first dielectric layer; and (g) thereafter depositingmetallic conduction layers in contact with said first conductionportions through said openings, said metallic conduction layers beingseparated from said second conducting portions.
 2. A method according toclaim 1, wherein during forming said first conducting portions incarrying out step (a), third conducting portions are formed on saidsubstrate at a level below said first and second conducting portions,said third conducting portions having arbitrary dimensions and havingupper surfaces at a level lower than said upper surfaces of said firstconducting portions, and wherein conducting lines are formed in contactat one end to said third conducting portions and at a second end tocontact levels including at least one of said appendices, saidconducting lines at said contact levels having upper surfacessubstantially coplanar to said upper surfaces of said first conductingportions.
 3. A method according to claim 2, wherein said level of saidthird conducting portions is formed sufficiently below said first andsecond conducting portions to require at least one step between saidthird conducting portions and said contact levels.
 4. A method accordingto claim 2, wherein said uniform thickness Hd of said first dielectriclayer is selected as a function of heights Hm of said first conductiveportions and of the difference Hl between the thicknesses of said seconddielectric layer by the relation

    Hd=Hm.sup.2 (Hm-Hl).sup.-1

and wherein a ratio s between said rate of etching said first dielectriclayer and said rate of etching said second dielectric layer in said step(f) satisfies the condition

    s=(Hd-Hm)Hl.sup.-1 >1.


5. A method according to claim 2, wherein said dimension W₁ is less thanor equal to W₂ /2, where W₂ is a smallest of dimensions of said secondconducting portions.
 6. A method according to claim 2, wherein upon saidstep (f) being carried out to form said openings, then second conductingpatterns are formed for interconnecting some of said first conductingpatterns, said second conducting patterns having contact zones for saidfirst conducting portions and said appendices at said conducting lines.7. A method according to claim 6, wherein said steps (a) through (g) arerepeated at least one.
 8. A method according to claim 1, wherein saidfirst dielectric layer is formed from one of silica (SiO₂) or siliconnitride (Si₃ N₄), and wherein said second dielectric layer is formedfrom polyimide or photoresist.
 9. A method according to claim 1, whereinsaid first conducting portions include micron patterns, said secondconducting portions include electrodes of active elements orinterconnection lines, and wherein said third conducting portionsinclude electrodes of active non-planar elements.
 10. A method accordingto claim 9, wherein said micron patterns include gates of field effecttransistors or emitters of bipolar transistors, and wherein said activenon-planar elements include bases or collectors of bipolar transistors.11. A method according to claim 1, wherein said uniform thickness Hd ofsaid first dielectric layer is selected as a function of heights Hm ofsaid first conductive portions and of the difference Hl between thethicknesses of said second dielectric layer by the relation

    Hd=Hm.sup.2 (Hm-Hl).sup.-1

and wherein a ration s between said rate of etching said firstdielectric layer and said rate of etching said second dielectric layerin said step (f) satisfies the condition

    s=(Hd-Hm)Hl.sup.-1 >1.


12. A method according to claim 1, wherein said dimension W₁ is lessthan or equal to W₂ /2, where W₂ is a smallest of dimensions of saidsecond conducting portions.
 13. A method according to claim 1, whereinupon said step (f) being carried out to form said openings, then secondconducting patterns are formed for interconnecting some of said firstconducting patterns, said second conducting patterns having contactzones for said first conducting portions and said appendices at saidconducting lines.
 14. A method according to claim 13, wherein said steps(a) through (g) are repeated at least one.